Design of PLL Frequency Synthrsizer for Data Link Communication

Sang-Chul Kwon^*·Kyung-Sik Kang^**

^*Corp. Ace Antenna.
^**Department of Industrial Management Engineering, Myongji University

^†Corresponding Author : Kyung-Sik Kang, Industrial and Engineering, Myongji University, Yongin 449-728, Korea, E-mail : kangks@mju.ac.kr

Abstract

For the first time, PLL frequency synthesizer using DDS was adapted for the data link communication system which should fast transmit and receive each other with the correct information and fast Hopping System. It is inevitable to lost the synchronization by slow lock time about PLL and no cut off the noise. This paper propose the design of PLL frequency synthesizer which can make 800MHz frequency range. The PLL frequency synthesizer has three high qualities those are frequency accuracy, fast lock time and outstanding phase noise.

데이터링크 통신을 위한 PLL 주파수합성기 설계

권 상 철^*·강 경 식^**

^*에이스안테나 방산 연구소
^**명지대학교 산업경영공학과

초록

Figure

Table

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Design of PLL Frequency Synthrsizer for Data Link Communication

Abstract

데이터링크 통신을 위한 PLL 주파수합성기 설계

초록

Figure

Table

Online Submission

KSSM

Editorial OfficeContact Information

Editorial Office
Contact Information